As electronic memories approach limits beyond which they will no longer be able to produce the density/cost/performance improvements so famously set forth in Moore's law, a host of memory technologies are being investigated as potential replacements for conventional silicon complementary metal oxide semiconductor (CMOS) integrated circuit memories.
Among the memory technologies being investigated are a number of bidirectional memory technologies: memories that exploit a directional characteristic of the material used to program or read a memory device. That is, conventional memory devices typically associate one of two memory states with the presence or absence of charge, or with a high or low voltage, for example. In conventional memories such as this, memory states are associated with uni-directional characteristics; charge is either present or not (e.g., DRAM, FLASH) or a node is held at a high or low voltage (e.g., SRAM). There is no sense of “direction” to such storage mechanisms. In contrast, bidirectional memories employ some directional aspect of their memory material to store binary information. For example, one memory state may be written by forcing a current through a bidirectional memory device in one direction or applying a voltage of one polarity, and another memory state may be written by forcing a current through the same device in the opposite direction or applying a voltage of the opposite polarity. The programmed memory states may then be sensed by, for example, applying to the memory device either a voltage to measure current related to memory state, or forcing a current through and measuring a voltage related to memory state.
Bidirectional memory types include resistive random access memories and magneto-resistive random access memories (both referred to as RRAM), programmable metallization cells, Pnictide phase change memories, polymer memories, ferro-electric random access memories (FeRAM), ionic memory devices and metal nano-particle memory cells.
An RRAM cell may be programmed, respectively, to high resistance and low resistance values by applying electric pulses of opposite polarities to a cell. The cell's high and low resistance values are employed to represent two different memory states. RRAM memories are known and described, for example, in a paper by W. W. Zhuang et al, presented at the 2002 International Electron Device Meeting (IEDM), entitled, “Novell Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM),” which is hereby incorporated by reference.
Programmable metallization cells utilize electrochemical control of nanoscale quantities of metal in thin films of solid electrolyte. Information is stored via electrical changes caused by the oxidation of a metal and reduction of metal ions in the solid electrolyte. Such an electrical change may be induced by applying a small electrical bias to a cell. A reverse bias will reverse the oxidation until the electrodeposited or electro-plated metal has been removed, thereby returning the cell to the original memory state. Programmable metallization cells are known and discussed, for example, in a paper entitled “Non-Volatile Memory Based on Solid Electrolytes,” by Michael N. Kozicki, et al, in an article entitled “Bipolar and Unipolar Resistive Switching in Cu-Doped SiO2,”, and by Christina Schindler et al. in IEEE Transactions on Electron Devices 54: 2762-2768, and in “Programmable Metallization Cell Memory Based on Ag—Ge—S and Cu—Ge—S Solid Electrolytes” by Michael N. Kozicki et al, available from the Institute of Electrical and Electronics Engineers, which papers are hereby incorporated by reference.
Polymer memories exhibit electrical bistability involving an increase in conductivity when a bias voltage of sufficient magnitude is applied to a cell. The cell may be returned to a low conductivity state by applying a bias voltage of the opposite. polarity to the device. Polymer memories are known and described, for example, in “Polymer Memory Device Based on Conjugated Polymer and Gold Nanoparticles,” by Ankita Prakash et al, published by the American Institute of Physics in 2006, which is hereby incorporated by reference.
Ferroelectric random access memories (FeRAMs) employ ferroelectric capacitors to store data. A voltage pulse of one polarity is used to program a cell to one memory state and a voltage pulse of opposite polarity may be employed to program the cell to another memory state. FeRAMs are known and described in “A Survey of Circuit Innovations in Ferroelectric Random-Access Memories,” by Ali Sheikholeslami et al, published in The Proceedings of the IEEE, Vol. 88, No. 5, May 2000, which is hereby incorporated by reference.
Bidirectional memory cells may be arranged in rectangular arrays in which individual memory cells are located at the intersection of row and column address lines, where one line is placed above the other. Individual cells are accessed (that is, read from or written to) by asserting the row address line and column address line that uniquely define a cell's location within the array. Or, for greater bandwidth, more than one column may be selected in parallel onto one row line, where each column line has separate read and write circuitry. Although an individual cell may be uniquely addressed by assertion of a row and column address line pair, because a plurality of memory cells share a row address line and a plurality of cells share a column address line (cells do not share row and column address lines), a plurality of cells may be “partially” selected by the assertion of a row or column address line.
That is, if, for example, a memory cell is selected by raising the voltage of its column address line and lowering the voltage of its row address line, all cells that share the selected column address line will have the voltage of their column address line raised and all cells that share the selected row address line will have the voltage of their row address line lowered and, in that sense, these non-selected cells will be partially selected.
Such partial selection poses the risk of inadvertently accessing one or more memory cells in addition to the targeted memory cell. Such inadvertent access could jeopardize the validity of the memory's data through an illegitimate read or write operation, sometimes characterized as a mis-read or mis-write. Current leakage paths may exacerbate the risk of inadvertent accesses. Such partial selection, leakage paths, and the attendant risks of inadvertent cell access, may be substantially eliminated, for example, by employing a pair of transistors at each cell location to uniquely access each memory cell. However, the addition of such selection transistors at each memory cell imposes a significant penalty in the form of increased memory cell area. A method and apparatus that provides bi-directional write access to a uniquely select a memory cell in an array that also prevents inadvertent access of bidirectional memory cells without significantly increasing the area of such a memory cell would therefore be highly desirable.